Publications

Book Chapters and International Journals

01) M. Boubekeur, D. Hickey, J. Mc Enery  and M. Schellekens, "A new Approach for Modular Average-Case Timing of Real-Time Java Programs", WSEAS Transactions on Computers, Issue2, Volume 1, December 2006, ISSN: 1991-8755.

02) M. Boubekeur, D. Hickey and M. Schellekens, "Evaluation of MOQA Average-Case Timing Results on a Real Time Platform", under review in ENTCS, Elsevier's series "Electronic Notes in Theoretical Computer Science" (http://www.entcs.org/)

03) D. Borrione, M. Boubekeur, et al. "VLSI-SOC: From Systems to Chips". Chapter:"Validation of Asynchronous Specifications using IF/CADP", Kluwer-Springer, 2006, ISBN: 0-387-33402-5

04) M. Boubekeur, D. Borrione, et al. "Languages for System Specifications. Selected Contributions on UML, SystemC, System Verilog, Mixed-Signal Systems, and Property Specifications from FDL'03". Chapter :" Modelling CHP descriptions in Labelled Transition Systems for an efficient formal validations of asynchronous circuit specifications" Ed. Grimm, Christoph. Kluwer Academic Publishers, 2004. ISBN: 1-4020-7991-5.

International conferences 

05) M. Boubekeur and M. Schellekens, "Automatic Optimization Techniques for Formal Verification of Asynchronous Circuits". Accepted for publication in the 14th IEEE International Conference on Electronics, Circuits and Systems (CECS07), December 11-14,  2007, Marrakech, Morocco.

06) J. Mc Enery, D. Hickey and M. Boubekeur. Empirical Evaluation of MainStream RTSJ Implementations: Java RTS & JamaicaVM. Accepted for publication in The 5th ACM International Workshop on Java Technologies for Real-time and Embedded Systems - JTRES 2007, September 2007, Vienna, Austria.

07) J. Connery, J. Mc Enery, D. Hickey and M. Boubekeur, "Profiling Real-time Java Applications". Accepted for publication in The IEEE International Conference on Computer Engineering & Systems (ICCES’07), Cairo, EGYPT, 2007,

08) M. Schellekens, R. Agarwal, A. Fedeli, Y. F. Lam, K. L. Man, M. Boubekeur and E. Popovici, "Towards Fast and Accurate Static Average-Case Performance Analysis of Embedded Systems: The MOQA Approach", Proc., 5th IEEE East-West Design and Test International Symposium, 2007.

09) K.L. Man, A. Fedeli, M. Mercaldi, M. Boubekeur and M.P. Schellekens, " SC2SCFL: Automated SC to SCFL Translation". SAMOS VII: LNCS International Symposium on Systems, Architectures, MOdeling and Simulation, Greece, July 16-19, 2007.

10) K. Man, M. Boubekeur and M. Schellekens, "Process Algebraic Approach to SystemVerilog". Accepted for publication in the 20th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2007), 22-26 April 20007, Vancouver, Canada. 

11) M. Boubekeur, K. Man and M. Schellekens, "Formal Verification of Mutual Exclusion between the Guards of Deterministic Choice Structures". 20th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2007), 22-26 April 20007, Vancouver, Canada.

12) M. Boubekeur, D. Hickey, J. Mc Enery and M. Schellekens, "Towards Modular Average-Case Timing in Real-Time Languages: An Application to Real-Time Java", Accepted for publication on the 6th WSEAS International Conference on APPLIED COMPUTER SCIENCE (ACS'06), Tenerife, December, 2006.

13) K.L. Man , M.P. Schellekens, M. Boubekeur, “Formal Specification and Analysis of Analog and Mixed-Signal Circuits Using Process Algebras for Hybrid Systems (with a focus on hybrid process algebra ACP^srt_hs”, in Proceedings of the IEEE International Soc Design Conference (ISOCC), Seoul, Korea, October, 2006.

14) M. Boubekeur, D. Hickey and M. Schellekens, "Evaluation of MOQA Average-Case Timing Results on a Real Time Platform", Proc of the conference Information of MFCSIT'06, Cork, August 2006.

15) M. Boubekeur, D. Borrione, et al. "Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications". Publ. in Forum on specification and Design Languages (FDL'03), Frankfurt, Germany, September 23-26, 2003.

16) D. Borrione, M. Boubekeur, et al. "Validation of asynchronous circuit specifications using IF/CADP". Publ. in 12th IFIP International Conference on Very Large Scale Integration (VLSI'03), Darmstadt, Germany, December 1-3, 2003.

17) D. Borrione, M. Boubekeur, et al. "An approach to the introduction of formal validation in an asynchronous circuit design flow". Publ. in 36th Hawai International Conference on Systems Science (HICSS'03), Hawaï, USA,January 6-9 , IEEE, 2003.

18) D. Borrione, M. Boubekeur, et al. "Introducing formal validation in an asynchronous circuit design flow". Publ. in The Fourth International Workshop on Designing Correct Circuits, Grenoble, France, April 6-7, 2002.

National Conferences (in French)

19) Menouer Boubekeur, "Etude de cas : vérification formelle d'un filtre asynchrone à l'aide de techniques de model-checking énumératif ". 6th Journées Nationales du Réseau Doctoral de Microélectronique, JNRDM' 03, Toulouse, 14-16 Mai 2003.

20) Menouer Boubekeur, "Une nouvelle approche pour la vérification formelle de circuits asynchrone". 3rd colloque en CAO de circuits et systèmes intégrés, CAO-GDR'02, Paris 15-17 Mai, 2002.

21) Menouer Boubekeur, "La vérification formelle de circuits asynchrone". 5th Journées Nationales du Réseau Doctoral de Microélectronique, JNRDM' 02, Grenoble, 23-25 Avril 2002.

Thesis

22) Menouer Boubekeur, "Formal Validation of Asynchronous Circuits Specifications: Methods and tools". PhD Thesis in Computer Science, University of Joseph Fourier. October, 2004. Grenoble. France.

23) Menouer Boubekeur, "Outils d'aide à la vérification formelle de systèmes infinis". Master Thesis in Computer Science, University of Joseph Fourier. June, 2000. Grenoble. France.

24) Menouer Boubekeur, "Placement of parallel data bases on an multiprocessor architecture" Engineer degree thesis, Computer sciences institute. University of Oran. October, 1997. Oran, Algeria.

Reports (in French)

25) Menouer Boubekeur, "Utilisation de l’environnement IF/CADP pour la vérification de circuits asynchrones". TIMA Laboratory, Grenoble. France.

26) Menouer Boubekeur, "Etude comparative entre deux méthodes de vérification de circuits asynchrones: méthode énumérative et méthode symbolique". TIMA Laboratory, Grenoble. France.

To contact Dr. M. Boubekeur

Email : menouer.boubekeur(at)cs.ucc.ie
Phone : + 353 (0)21 490 1918
Fax   : +353 (0)21 490 1908

CEOL, Lancaster Hall,

6 Little Hanover street,

Cork, Ireland.